Wednesday, April 1, 2009

Verilog: Source of brain clog

Earth hour has come and gone. I did my part by switching off my entire house lights. I went out to watch them switch kl and twin tower lights off. Then watched them switch it back on at 9.30pm(took a video of it too).

I don't have time to really blog about it now (but I will soon) as I have other obligations like ASSIGNMENTS. I have to write a verilog program and right now I'm stuck at how to write the output (I don't even know if my input's are written correctly). Furthermore, the verilog software I have just won't compile my source codes.

You see; I haven't done my 2nd lab for this subject which is about verilogs. So whatever I'm doing right now, is trial-and-error and referring to my lecture notes. I guess it's going to be another sleepless night for me. I'm TOTALED!!!

1 comment:

Anonymous said...

it happens to me too..just take one day at a time and get the best out of it..most importantly, you must be happie.

Post a Comment